1. Field of the Invention
This invention generally relates to semiconductor integrated circuit device seal structures which prevent the migration of contaminants from one side of the seal structure to the other. More particularly, the present invention relates to a continuous seal structure having electrically isolated conductive lines which lie in an underlying stratum of the integrated circuit structure.
2. Description of the Related Art
One problem common to all semiconductor integrated circuits is contamination by undesirable ionic species. The ions of certain contaminants, such as sodium, are mobile in silicon dioxide ("oxide") and drift through the oxide toward regions with a negative bias. These contaminants can interfere with the normal operation of semiconductor devices by giving rise to changes in device characteristics, leading to failure of the integrated circuit. It is for this reason that integrated circuit devices require a topside, passivation layer if they are to be encapsulated in standard, low-cost, plastic packages.
Various semiconductor integrated circuit devices have been developed which are user programmable. Devices such as programmable logic array (PLA) circuits, programmable read only memory (PROM) circuits, and the like, are designed and manufactured with an architecture that a user can program, or customize, to fit the user's specific application by blowing appropriate fuses. In addition, many types of integrated circuits, such as static random access memories (SRAM) and dynamic random access memories (DRAM), use programmable fuses to activate redundant circuit elements which can replace defective circuit elements of the integrated circuit. Thus, the manufacturer can increase the number of good die on a wafer after fabrication. As shown in FIG. 1, MOCHIZUKI et al., U.S. Pat. No. 4,413,272, discloses a typical prior art semiconductor device having a fuse.
One method used to program a fuse-programmable device involves the use of a laser to blow the appropriate fuses. A typical laser-programmable device is disclosed by REDFERN et al., U.S. Pat. No. 4,238,839.
In accordance with prior art processes, the blowing of fuses must be carried out in a clean room before the final sealing step of the fabrication process to prevent contaminants from depositing on the wafer and ultimately making their way to adjacent circuitry.
A problem that arises with testing and laser programming of devices is one of efficiency of production. Each laser-test station can handle only a relatively small number of wafers within any given time. Furthermore, as device density increases, the wafer testing time during programming increases. Hence, an increased number of laser-test stations are needed in the clean room in order to keep production time to a minimum. Each laser-test station takes up a certain amount of clean room area. Therefore, if a large number of laser test stations is necessary to meet production demands, a considerable amount of clean room area must be dedicated to laser-test equipment in addition to the area necessary for housing fabrication equipment. Clearly, costs would be reduced and production efficiency increased if laser equipment could be housed outside expensive clean room areas. To enable laser equipment to be housed outside the clean room, however, the problem of contaminants must be solved.
Furthermore, for integrated circuits using laser-fuse-redundancy schemes, the wafers having the dice fabricated thereon must actually be tested twice. First, they are tested and the requisite customizing fuses are blown prior to the passivation step of the fabrication process. Then, the wafers must be retested to separate good die from bad die after the final sealing processing is completed. If the laser-test operation could be done after the final sealing process, this retesting could be eliminated, thereby reducing wafer cost. This would require a structure that would maintain passivation integrity for the integrated circuit through laser testing.
One form of seal structure is disclosed in U.S. patent application Ser. No. 637,460 (HASKELL et al.), assigned to the common assignee of the present invention. In that disclosed device, electrically isolated conductive lines pass from circuit components to the fuses through seal regions which surround the fuses. This allows rupturing of the device's passivation layer above the fuses, while preserving the passivation integrity for the remainder of the device, viz., outside of the sealed regions. The seal regions formed according to HASKELL et al. maintain passivation integrity for the integrated circuit and permit a final passivation processing step after, rather than before, the programming of fuses. Additionally, the fabrication process is difficult due to relatively severe step coverage requirements needed to properly form the physical structures disclosed. Leakage currents can arise between the conductive lines and the substrate. Therefore, the HASKELL et al. structure is not suitable for all integrated circuits.
Hence, there remains a need for an integrated circuit seal structure which overcomes the deficiencies and limitations of the prior art.